可能不同2440平台時鐘頻率有所不同，設置方式卻是類似的，以下是我的u-boot時鐘設置部分整個過程解析：
這是第一處時鐘設置代碼：
/* Initialize System Clock, FCLK:HCLK:PCLK = 1:2:4,default FCLK is
120MHz */
ldr r0, =S3C24X0_CLOCK_POWER_BASE
mov r1, #3
str r1, [r0, #CLKDIVN_OFFSET]
MPLLCON_OFFSET = 0x14
可見0x4C000014:CLKDIVN被設置為0x03,它的意思是
HDIVN [1]
0: HCLK has the clock same as the FCLK.
1: HCLK has the clock same as the FCLK/2.
PDIVN [0]
0: PCLK has the clock same as the HCLK.
1: PCLK has the clock same as the HCLK/2.
即FCLK:HCLK:PCLK = 1:2:4
第二處時鐘設置代碼：
mov r2, #MDIV_405
add r2, r2, #PSDIV_405
str r2, [r0,#MPLLCON_OFFSET]
其中
#define MDIV_405 0x7f << 12
#define PSDIV_405 0x21
MPLLCON_OFFSET = 0x04
可見0x4c000004:MPLLCON被設置為0x007f021,它的意思是：
PLLCON Bit Description Initial State
MDIV [19:12] Main divider control 0x5C / 0x28
PDIV [9:4] Pre-divider control 0x08 / 0x08
SDIV [1:0] Post divider control 0x0 / 0x0
即：SDIV = 0x1, PDIV = 0x2, MDIV = 0x7f
Input Frequency Output Frequency MDIV PDIV SDIVN
12.0000MHz 405.00 MHz 127(0x7f) 2 1
由此可以算出FCLK = 405MHz, HCLK = 202.5MHz, PCLK = 101.25MHz
下面有個注意事項很有必要認真記住：
NOTES:
1. Although the MPLL starts just after a reset, the MPLL output (Mpll) is not used as the system clock until the software
writes valid settings to the MPLLCON register. Before this valid setting, the clock from external crystal or EXTCLKsource
will be used as the system clock directly. Even if the user does not want to change the default value of MPLLCON
register, the user should write the same value into MPLLCON register.
第三處時鐘設置代碼：
第三處是在C函數armboot_start裡調用int board_init (void)初始化化的，來看代碼:
int board_init (void)
{
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */
clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */
delay (4000);
/* configure UPLL */
clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */
delay (8000);